
ZTE's High Performance 5G Core Network UPF Implementation Based on 3rd Generation Intel® Xeon® Scalable Processors
This paper describes ZTE's 5G core network UPF solution based on the latest 3rd Gen Intel Xeon Scalable processors and Intel Ethernet 800 Series Network Adapters with Dynamic Device Personalization (DDP) capabilities.
This paper is a detailed study of how a virtualized Cable Modem Termination System (vCMTS) data-plane workload can take advantage of the advanced features of 3rd Gen Intel® Xeon® Scalable processor architecture enhancements such as bigger cache-sizes at each level, higher core-count, more memory, and specifically advanced features such as: Enhanced Intel® Advanced Vector Extensions 512 (Intel® AVX-512), Dual AES encryption engines, Intel® Vector AES New Instructions (AES-NI),
Intel® Vector PCLMULQDQ carry-less multiplication instruction, Intel® QuickAssist Technology. It also provides insights into implementation options and establishes an empirical performance data baseline that can be used to estimate the capability of a vCMTS platform running on industry-standard, high-volume servers based on 3rd Gen Intel Xeon Scalable processor architecture. Actual measurements are presented for a 3rd Gen Intel Xeon Scalable processor-based system. Results shown in the paper showcase a 70% improvement in vCMTS platform performance and service group density when utilizing the maximum core Network SKU of the 3rd generation Intel Xeon Scalable processor.
This solution snapshot illustrates how Yellow Messenger virtual assistant needed to inference an intent classification model in under 100 ms to provide customers with optimal experiences. Optimizing Yellow Messenger’s intent classification model on 3rd Gen Intel® Xeon® Scalable processors reduced inferencing time to less than 100 ms. Optimization cuts latency and speeds throughput, delivering real-time, intelligent responses for optimal customer experiences.
This solution snapshot illustrates how accelerating tuning on 2nd Gen Intel® Xeon® Scalable processors allowed
Nordigen needed to reduce the hyperparameter tuning time for their XGBoost model (part of the Scoring Insights product suite) in order to streamline their model search efforts. Nordigen to expand the parameter space and even run faster on 3rd Gen Intel Xeon Scalable processors.
This paper is the first in a series of white papers focusing on how to write packet processing software using the AVX-512 instruction set. It provides a brief overview of the Intel® AVX-512 instruction set and describes the microarchitecture optimizations for the instruction set in the latest 3rd Generation Intel® Xeon® Scalable Processors.
This solution brief provides an overview of the Intel® AVX-512 powerful SIMD instruction set, which has been optimized in the latest 3rd Generation processors with compelling performance benefits. The document sets the scene for a series of technology guides explaining how to get start writing packet processing software with the Intel® AVX-512 instruction set.

Intel® AVX-512 - Writing Packet Processing Software with Intel® AVX-512 Instruction Set Technology Guide
This paper is the second in a series of white papers that focuses on how to write packet processing software using the Intel® AVX-512 instruction set. This paper describes how Intel® AVX-512 optimizations are enabled in software development frameworks such as DPDK and FD.io. It includes examples of using Intel® AVX-512 in these frameworks as well as the performance benefits obtained, demonstrating performance gains in excess of 300% in micro-benchmarks.
This technology guide provides a brief overview of the technology advancements that minimize the impact of power state changes and improve usage in low-latency packet processing applications and broaden the use cases that can leverage per-core P-state power-saving technology.

Intel® Software Guard Extensions (Intel® SGX) - NGINX Private Key on 3rd Generation Intel® Xeon® Scalable Processor User Guide
This user guide provides directions for deploying NGINX workload to access the private key protected inside an Intel® Software Guard Extensions (Intel® SGX) enclave on a 3rd Generation Intel® Xeon® Scalable processor with production-fused CPU parts, using the Public-Key Cryptography Standard (PKCS) #11 interface and OpenSSL. The user guide includes Ansible scripts to automate the system set up.

Intel® Software Guard Extensions (Intel® SGX) – Key Management on the 3rd Generation Intel® Xeon® Scalable Processor Technology Guide
The document provides an overview of Intel® Software Guard Extensions (Intel® SGX) technology and how developers can partition security sensitive code and data into an Intel protected SGX enclave on the 3rd Generation Intel® Xeon® Scalable platform. The guide focuses on the use of SGX to secure NGINX application private keys. The guide also introduces the Key Management Reference Application (KMRA), a subsystem enabling customer private key protection, in multiple use cases.

3rd Generation Intel® Xeon® Scalable Processor - Achieving 1 Tbps IPsec with Intel® Advanced Vector Extensions 512 (Intel® AVX-512) Technology Guide
The document describes how the latest Intel® Advanced Vector Extensions 512 (Intel® AVX-512) instructions and Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI) enabled in the latest Intel® 3rd Generation Xeon® Scalable Processor are used to significantly increase and achieve 1 Tb of IPsec throughput.
This document describes how Intel® Speed Select Technology – Core Power (Intel® SST-CP), which is available in selected models of the most recent generation of Intel processors, offers dynamic prioritization of CPU core power/frequency by assigning each CPU core a priority and attempting to satisfy the requirements of each CPU core in priority order. This Lets you control and direct base frequency, essentially allowing you to power-up and prioritize power/frequency for your most critical workloads at the most critical times.
Review Intel offering for OpenSSL framework underlying crypto technologies such as Intel® QuickAssist Technology, Intel® AES New Instructions (Intel® AES-NI) and AVX-512 Vector AES (VAES) instructions on the Intel® architecture platform.
This document describes how Cloudify orchestration, Kubernetes cloud technologies, and High Performance Computing are merging in Financial Services workloads optimized for 3rd Generation Intel Xeon Scalable Processors.
This document provides instructions for the installation and configuration of CRI Resource Manager, describes its functionality, and discusses possible usage scenarios. It is intended for bare-metal cluster operators wanting to capitalize on the full potential of the latest Intel® Xeon® Scalable processors.
Intel Select Solutions for NFVI Forwarding Platform are verified
configurations of compute, network, storage, and middleware elements
for packet-processing-intensive network workloads that can significantly
accelerate time to production and reduce TCO.
Intel Select Solutions for vRAN provide pre-validated reference architectures
that help accelerate development for virtualized RAN architectures. Tailored
hardware based on the flexible performance of the 3rd Generation Intel Xeon Scalable processors is complemented by a software stack based on Wind River Studio.
Intel Select Solutions for vRAN provide pre-validated reference architectures that help accelerate development for virtualized RAN architectures. Tailored hardware based on the flexible performance of the 3rd Generation Intel Xeon Scalable processors is complemented by a software stack based on Red Hat Enterprise Linux.
Intel Select Solutions for vRAN provide pre-validated reference architectures that help accelerate development for virtualized RAN architectures. Tailored hardware based on the flexible performance of the 3rd Generation Intel Xeon Scalable processors is complemented by a software stack based on VMware Telco Cloud Platform.
Tests of virtual broadband network gateways (vBNG) using 3rd generation Intel® Xeon® Scalable processors show up to 20% better performance and up to 56% improvement in performance per dollar processor spending compared to the previous CPU generation.